DIV tests - available ST docs simply say '2-17 cycles'

Legend
	Decode
	Execute
	Fetch
	Flush
	Fetch Stall - space in prefetch buffer but bus busy
	Decode Stall - bus busy
	Decode Stall - insufficient data in prefetch buffer
	Decode Stall - read after write

The stated cycle count would seem to imply binary long division and this is how the STM8 emulator in ucsim currently treats div for. cycle counting. However the cycles measured on actual hardware suggest this is not correct.

Address	Instruction	1	2	3	4	5	6	7	8

0x08100	ldw X,#0x8000
0x08103	ld A,#0x80
0x08105	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08108	ldw X,#0x8000
0x0810b	ld A,#0x40
0x0810d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08110	ldw X,#0x8000
0x08113	ld A,#0x20
0x08115	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08118	ldw X,#0x8000
0x0811b	ld A,#0x10
0x0811d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08120	ldw X,#0x8000
0x08123	ld A,#0x08
0x08125	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08128	ldw X,#0x8000
0x0812b	ld A,#0x04
0x0812d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08130	ldw X,#0x8000
0x08133	ld A,#0x02
0x08135	div X,A

Address	Instruction	1	2	3	4	5	6

0x08138	ldw X,#0x8000
0x0813b	ld A,#0x01
0x0813d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08140	ldw X,#0x8000
0x08143	ld A,#0x80
0x08145	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08148	ldw X,#0x4000
0x0814b	ld A,#0x80
0x0814d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08150	ldw X,#0x2000
0x08153	ld A,#0x80
0x08155	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08158	ldw X,#0x1000
0x0815b	ld A,#0x80
0x0815d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08160	ldw X,#0x0800
0x08163	ld A,#0x80
0x08165	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08168	ldw X,#0x0400
0x0816b	ld A,#0x80
0x0816d	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08170	ldw X,#0x0200
0x08173	ld A,#0x80
0x08175	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x08178	ldw X,#0x0100
0x0817b	ld A,#0x80
0x0817d	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x08180	ldw X,#0x0080
0x08183	ld A,#0x80
0x08185	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x08188	ldw X,#0x0040
0x0818b	ld A,#0x80
0x0818d	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x08190	ldw X,#0x0020
0x08193	ld A,#0x80
0x08195	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x08198	ldw X,#0x0010
0x0819b	ld A,#0x80
0x0819d	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x081a0	ldw X,#0x0008
0x081a3	ld A,#0x80
0x081a5	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x081a8	ldw X,#0x0004
0x081ab	ld A,#0x80
0x081ad	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x081b0	ldw X,#0x0002
0x081b3	ld A,#0x80
0x081b5	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x081b8	ldw X,#0x0001
0x081bb	ld A,#0x80
0x081bd	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x081c0	ldw X,#0x0000
0x081c3	ld A,#0x80
0x081c5	div X,A

Address	Instruction	1	2	3	4	5	6	7	8	9

0x081c8	ldw X,#0x003f
0x081cb	ld A,#0x08
0x081cd	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x081d0	ldw X,#0x0040
0x081d3	ld A,#0x08
0x081d5	div X,A

Address	Instruction	1	2	3	4	5	6	7	8

0x081d8	ldw X,#0x0041
0x081db	ld A,#0x08
0x081dd	div X,A

Address	Instruction	1	2	3	4	5	6	7

0x081e0	ldw X,#0x8000
0x081e3	ldw Y,#0x0001
0x081e7	divw X,Y