PM0044 5.4 Conventions, table 3

Legend
	Decode
	Execute
	Fetch
	Flush
	Fetch Stall - space in prefetch buffer but bus busy
	Decode Stall - bus busy
	Decode Stall - insufficient data in prefetch buffer
	Decode Stall - read after write

Errata

The LDW shown in PM0044 table 3 is missing a decode cycle.
(Confirmed on HW)
The ADDW shown in PM0044 table 3 has one too many decode cycles.
(Confirmed on HW)
The LD shown in PM0044 table 3 is missing a decode cycle.